A Circuit Technique for Variability- Aware Design of an Sram Cell
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چکیده
The primary motivation behind aggressive device scaling is to achieve improved performance and increased integration. These improvements come at the cost of increased sensitivity to PVT variations and standby leakage, particularly in area-constrained circuit such as SRAM that employs minimum-geometry devices. An attempt is made in this work to mitigate these problems in traditional 6T SRAM cell by incurring minimum area penalty and retaining its fully differential architecture. This chapter presents a technique to mitigate the impact of PVT variations on design metrics of TG8T (transmission gate-based eight transistor) SRAM Cell after briefly introducing the metrics and challenges in designing nanoscaled SRAM.
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